1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more specifically, to a structure of a semiconductor integrated circuit device in which a dynamic semiconductor memory device (hereinafter referred to as a DRAM) and a logic circuitry are mounted together on one chip.
2. Description of the Background Art
Currently, various semiconductor devices such as microcomputers, memory and gate arrays are mounted on electric appliances including personal computers and work stations. Especially, as portable personal computer equipments for multi-media applications have come into wide use, a semiconductor integrated circuit device in which a memory of a large storage capacity is mounted on a system chip has been developed.
Such a semiconductor device has a pad for exchanging signal or data with the outside of the device. When the semiconductor device is sealed in a package, the pad is connected to an external pin terminal. If the semiconductor device is formed on the same chip or wafer as other semiconductor devices, the pad is coupled to an internal line.
There is a large load on the pad for outputting a signal or data, dependent on an input capacitance and line capacitance of the external device. Accordingly, a driver circuit (output buffer circuit) having large current drivability is provided for the output pad, as it needs stored information or signal formed in the device.
Especially when the semiconductor device is sealed in a package and mounted on an electric product, for example, the pin terminal of the semiconductor device is connected to a printed line or the like on the board on which the device is mounted. Further, input capacitance of another semiconductor integrated circuit device connected to the pin terminal and storage capacitance of the printed line are large, it is necessary to charge/discharge the load capacitances (parasitic capacitances) having relatively large capacitance values in a prescribed time period. Therefore, it is necessary that the output buffer circuit (driver circuit) has sufficiently larger current drivability than the current drivability of internal circuitry.
FIG. 29 is a schematic block diagram showing the structure of a system chip 2000 having a DRAM such as described above.
System chip 2000 shown in FIG. 29 has a logic LSI for performing logic processing and a memory LSI for storing data formed on the same chip.
Referring to FIG. 29, system chip 2000 includes a logic processing portion and a memory portion. Commonly to the logic processing portion and a memory portion, there is provided an input/output buffer circuit 400 for input/output of data and signals from and to the outside of the device.
Logic processing portion includes a logic circuit 402 for receiving data and/or signals from input/output buffer circuit 400 and the memory portion, which will be described later, and for performing prescribed processing.
The memory portion includes a memory cell array having dynamic memory cells arranged in a matrix, a DRAM control circuit 404 for controlling access to the memory cell array 406, a word line driver 408 for driving a row (word line) of memory cell array 406 to a potential of a selected state under control of DRAM control circuit 404, a sense amplifier 410 for detecting, amplifying and latching data of a memory cell connected to a selected row in memory cell array 406, and a column decoder 414 for selecting a column of memory cell array 406 under control of DRAM control circuit 404.
The memory portion further includes a voltage converting circuit 412 lowering an external power supply voltage Vcc and supplying an internal power supply voltage to be supplied to DRAM control circuit 404, sense amplifier 410 and so on, and a Vpp generating circuit 416 receiving the external power supply voltage Vcc and generating a boosted potential to be supplied to word line driver circuit 408.
Commonly to input/output buffer circuit 400, logic circuit 402, Vpp generating circuit 416 and voltage converting circuit 412, a power supply line 142 is provided. The power supply line 142 is supplied with an external power supply voltage Vcc from power supply pad 140.
Meanwhile, commonly to input/output buffer circuit 400, logic circuit 402, DRAM control circuit 404, word line driver circuit 408, sense amplifier 410, sense amplifier 410, memory cell array 406 and column decoder 414, a ground power supply line 146 is provided. To the ground power supply line 146, a ground potential GND is supplied through a power supply pad 144.
The structure and operation of input/output buffer circuit 400 in system chip 2000 having such a structure as shown in FIG. 29 will be described.
FIG. 30 is a schematic block diagram showing a structure of an output buffer in a conventional semiconductor memory device disclosed, for example, in Japanese Patent Laying-Open No. 61-294929.
Referring to FIG. 30, in this structure also, the output buffer circuit includes a p channel MOS transistor 3 connected between a power supply load la receiving power supply voltage Vcc and an output node 2; an n channel MOS transistor 4 connected between output node 2 and a ground node lb receiving ground voltage GND; an NAND circuit 5 receiving an internal read data dl and a data output enable signal ZOE applied through an inverter 7; and an NOR circuit 6 receiving the internal read data d1 and the data output enable signal ZOE.
An output signal from NAND circuit 5 is applied to the gate of MOS transistor 3, and an output signal from NOR circuit 6 is applied to the gate of MOS transistor 4.
There is a relatively large parasitic capacitance CL at output node 2.
Operation of the output buffer circuit shown in FIG. 30 will be described with reference to the diagram of wave forms shown in FIG. 31.
Internal read data d1 changes from an intermediate potential corresponding to a standby state, to the L level. When data output enable signal ZOE is at the "H" level, the output signal from inverter 7 is at the "L" level, the output signal from NAND circuit is at the "H" level and the output signal from NOR circuit 6 is at the "L" level.
Therefore, MOS transistors 3 and 4 are both off, and output buffer circuit is set to an output high impedance state (Hi-Z).
At time TO, when data output enable signal ZOE attains to the active state of "L" level, the output signal from inverter 7 attains to the "H" level, and NAND circuit 5 and NOR circuit 6 both function as inverters. Therefore, output signals from NAND circuit 5 and NOR circuit 6 both attain to the "H" level, and in response, MOS transistor 3 turns off and MOS transistor 4 turns on.
Therefore, output node 2 is coupled, through the MOS transistor which is on, to the ground node lb and is discharged. Consequently, external read data d1 falls from the high impedance state Hi-Z to the level of the ground potential.
At time T1, when data output enable signal ZOE attains to the "H" level, regardless of the logic level of internal read data D1, output signals from NAND circuit 5 and NOR circuit 6 attain to the "H" level and "L" level, respectively, and the output buffer circuit again attains to the high impedance state.
Thereafter, when another memory cell is selected, data of the "H" level is read and internal read data d1 attains to the "H" level, and data output enable signal ZOE again attains to the "L" level at time T2.
In this state, NAND circuit 5 and NOR circuit 6 again function as inverters, and output signals from these circuits 5 and 6 attain to the "L" level. Accordingly, MOS transistor 3 turns on, and MOS transistor 4 turns off. In response, output node 2 is charged to the level of the power supply voltage Vcc through MOS transistor 3 which is on, and external read data D1 attains to the "H" level.
At time T3, when data output enable signal ZOE again attains to the "H" level, the output buffer circuit is again set to the output high impedance state.
FIG. 32 shows an example of the power supply line and ground line of system chip 2000.
In FIG. 32, the memory portion and the logic portion will be generally referred to as internal circuitry 11.
Referring to FIG. 32, for internal circuitry 11 performing prescribed processing operation and generating internal read data d1 and for output buffer circuit 12, power supply line 10a and ground line 10b are commonly provided.
To the power supply line 10a, power supply potential Vcc is transmitted, and to ground line 10b, ground potential GND is transmitted. When read data signal D1 from output buffer circuit 12 changes from the "L" level to the "H" level, current is supplied from power supply node 1a to output node 2 through MOS transistor 3 as shown in FIG. 30. Output buffer circuit 12 charges large parasitic capacitance CL existing at the output node 2 at high speed, and therefore, MOS transistors 3 and 4 have high current drivability.
Therefore, in such a case as described above, when read data signal D1 from output buffer circuit 12 rises from "L" level to "H" level, current on the power supply line 10a is consumed abruptly, and power supply voltage Vcc on power supply line 10a lowers by about 0.5 V, for example.
When read data signal D1 from output buffer circuit 12 lowers from the "H" level to the "L" level, MOS transistor 4 shown in FIG. 30 is rendered conductive, a large current is quickly discharged from output node 2 to ground node 1b. In this case, because of the large current abruptly discharged from output buffer circuit 12, the potential level of ground line 10b rises by about 0.5 V, for example.
Power supply noise (noise of power supply voltage and ground voltage, respectively) on power supply line 10a and ground line 10b is transmitted to internal circuitry 11. When power supply voltage Vcc is about 5 V, for example, the power supply noise is about 1/10 of the power supply voltage Vcc and relatively small. Therefore, malfunction caused by the power supply noise is not a problem in internal circuitry 11.
However, as the degree of integration of semiconductor devices has been increased recently, generally the potential level of power supply voltage Vcc is lowered to 3.3 V or lower, in order to reduce power consumption and to realize high speed operation. In that case, the power supply noise of 0.5 V is about 1/6 of the power supply voltage Vcc. Therefore, there is caused a problem that internal circuitry malfunctions because of the power supply noise, and a signal of "H" level may be erroneously determined to be "L" level or a signal at the "L" level may be erroneously determined to be "H" level signal.
In order to absorb the power supply noise mentioned above, generally decoupling capacitances C1 and C2 are provided near internal circuitry 11 and output buffer circuit 12, respectively, for stabilization, as shown in FIG. 34.
Decoupling capacitances C1 and C2 are connected between power supply line 10a and ground line 10b. When output buffer 12 operates and consumes current on power supply line 10a and power supply voltage Vcc lowers, positive charges stored in decoupling capacitance C2 are supplied to power supply line 10a, suppressing lowering of the power supply voltage Vcc.
Meanwhile, when output buffer circuit 12 operates and discharges current to the ground line 10b, the discharged current is absorbed by decoupling capacitance C2, suppressing rise in the ground voltage GND.
Decoupling capacitance C1 provided near internal circuitry 11 suppresses power supply noise of voltages vcc and GND to internal circuitry 11, and further, power supply noise caused by the operation of output buffer 12 can be prevented from being transmitted to internal circuitry 11.
It is necessary for the decoupling capacitance to suppress power supply noise by the stored charges (positive and negative charges). Therefore, in order to suppress lowering of power supply voltage Vcc and rise of the ground voltage GND, it is necessary that the decoupling capacitance has a capacitance value of several hundreds pico farad, for example about 450 pF.
By the decoupling capacitances C1 and C2, power supply.line 10a and ground line 10b are capacitively coupled. The power supply voltage Vcc on power supply line 10a lowers quickly, and it changes in alternate manner. Therefore, as shown in FIG. 35, because of the decoupling capacitance C2, power supply line 10a and ground line 10b are coupled in alternating manner, lowering of potential of power supply voltage Vcc is transmitted to ground line 10b, and ground voltage GND lowers.
Decoupling capacitances C1 and C2 absorb rise of the ground voltage GND by the stored load. Therefore, when ground voltage GND lowers, it is not possible to absorb the lowering of potential by the decoupling capacitances C1 and C2.
Under such circumstances, there will be a following problem when the internal circuitry 11 is a circuit for driving the memory cell array, for example.
FIG. 36 shows a memory cell structure. Referring to FIG. 36, memory cell MC includes an access transistor QM formed of an n channel and MOS transistor having one conduction node connected to a bit line BL, the other conduction node connected to a storage node SN and a gate connected to a word line WL, and a memory cell capacitor CM having one electrode connected to the storage node SN and the other electrode receiving a cell plate potential Vcp. Generally, cell plate potential Vcp is held at an intermediate potential level of (Vcc+GND)/2. Memory information is stored in the form of charges at storage node SN.
Assume, as an example, that the word line WL is not selected and its potential is 0 V. When output buffer circuit 12 is in operation, bit line BL is connected to a selected word line (word line WL' which is different from the shown word line WL), and in accordance with the data stored in a memory cell connected to the bit line BL, it is set to the "H" level or "L" level.
In the following, it is assumed that the potential of bit line BL is at the "L" level, that is, 0 V. At that time, referring to FIG. 35, when output buffer operates and the power supply voltage Vcc lowers, the ground voltage GND lowers correspondingly. The lowering of the ground voltage GND is transmitted to internal circuitry 11 as shown in FIG. 34, and the potential 0 V of the bit line BL electrically connected to the output buffer circuit 12 is shifted to the negative potential side. Meanwhile, since the potential of word line WL is at 0 V, the potential difference between the gate and source of memory cell transistor QM will be larger than 0 V. Consequently, memory cell transistor QM is rendered weakly conductive, and charges (positive charges) stored in storage node SN are discharged to bit line BL. More specifically, stored charges of a memory cell which is not selected reduces, degrading data retention characteristic of the memory cell. In the worst case, data stored in a non-selected memory cell may possibly be destroyed.
Assume that the selected memory cell holds stored data at the "H" level and the potential of the bit line BL is held at the level of the power supply voltage Vcc. When the potential Vcc of the bit line BL lowers because of power supply noise in this state, the potential level of write data at the "H" level of the selected memory cell lowers, and it becomes impossible to store necessary charges in storage node SN. In this case, at the time of writing or restore of the data at the "H" level, amount of charges at the storage node SN reduces, degrading charge retention characteristic of the memory cell.
The charge retaining characteristic of the memory cell while the output buffer circuit is in operation as described above is referred to as dynamic refresh characteristic. On the other hand, charge retention characteristic of the memory cell while the output buffer circuit or the like is not in operation is referred to as a static refresh characteristic. Generally, since leak current of a memory cell transistor increases because of the influence of power supply noise as described above, dynamic refresh characteristic is degraded from the static refresh characteristic. Especially in a memory cell relatively close to the output buffer circuit or when the substrate bias (negative potential) has a small absolute value, the degree of degradation is considerable.
In the output buffer circuit 12, when ground voltage GND on ground line 12b lowers, the potential difference between the gate and the source of MOS transistor 4 for driving to the "L" level becomes larger, the MOS transistor is weakly turned on, and current flows from output node 2 to ground node 1b. Consequently, potential level of power supply voltage Vcc further lowers, the ground potential GND also lowers correspondingly, and power supply noise becomes larger. Further, potential level of read data signal D1 also lowers, making it difficult to read data correctly.
Further, at this time, current flows from the power supply node 1a to the ground node 1b through MOS transistors 3 and 4, causing the problem of increased current consumption in the output buffer circuit.
In a semiconductor memory device, the number of bits of input/output data tends to be increased, the number of output buffer circuits also tends to increase accordingly, and power supply noise of the output buffer circuit tends to be larger. In a semiconductor integrated circuit device such as a logic circuit, the number of output signals tends to be increased as the degree of integration becomes higher, the number of buffer circuits also tends to increase accordingly, and the problem of power supply noise similarly becomes more serious.
In order to make smaller the power supply noise mentioned above, what is necessary is to lower the speed of charging/discharging the output node 2. However, in that case, the data output speed also lowers, and as a result, it becomes impossible to provide output signals of data at high speed.
As a method of suppressing degradation of dynamic refresh characteristic, the potential level of the word line which is at a standby state may be set to a negative potential. More specifically, when the potential level of the word line is lower than the bit line BL which is at the ground potential, it is possible to prevent memory cell transistor QM from being rendered weakly conductive, even when the potential level of the bit line lowers because of the power supply noise.
FIG. 37 is a schematic block diagram showing a structure of a potential setting circuit 100 which can apply a negative potential to a word line WL which is not selected, disclosed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL30, No.11 NOVEMBER 1995 pp.1183.about.1188.
Potential setting circuit 100 includes a decoder circuit 114 responsive to an address signal for setting a low selection signal RS to an active state ("L" level); a pair of p channel MOS transistors 102 and 104 both receiving an internal boosted potential Vpp at their sources and having gates and drains connected to each other; a pair of n channel MOS transistors 106 and 108 receiving a negative potential Vn at their sources, having gates and drains connected to each other and having drains connected to the drains of p channel MOS transistors 102 and 104, respectively; an n channel MOS transistor 110 connected between the drain of p channel MOS transistor 104 and an output node of decoder circuit 114 and having its gate potential fixed at the potential Vcc; and a p channel MOS transistor 112 connected between the drain of n channel MOS transistor 108 and the output node of decoder circuit 114 and having its gate potential fixed at the potential GND.
The word line WL is connected to a node between the drain of transistor 102 and drain of transistor 106.
However, in the potential setting circuit 100, while the word line WL is not selected and a negative potential is applied, the negative potential Vn is applied to the gate of transistor 104 and the internal boosted potential Vpp is applied to the source of transistor 104, degrading reliability of the gate insulating film of the transistor.
Further, when this circuit is to be mounted on a system chip together with a DRAM, there will be the following problem.
More specifically, when an LSI having a DRAM and a circuit for performing a prescribed logic operation on the data output from DRAM both formed on the same chip is to be manufactured, thicknesses of an oxide film of MOS transistors constituting the DRAM and the logic operation circuit are generally set to a common thickness.
More specifically, assume that a chip having aforementioned elements mounted together is manufactured through a process flow for manufacturing the DRAM. In the DRAM, in order to write "H" level completely in the memory cell, boosted level (hereinafter referred to as Vpp) is necessary as the voltage to be supplied to the selected word line, and in order to ensure reliability of the gate oxide film, the thickness of the oxide film should be thick. However, thick oxide film causes degradation in speed of operation of MOS transistors which are required of high speed operation.
The aforementioned boosted level Vpp is supplied not only to the selected word line. For example, when a so-called shared sense amplifier structure is employed, for conduction between the bit line in the memory cell array and the transfer gate transistor of the bit line in the sense amplifier, it is necessary to supply the boosted level to the gate. In that case also, it is necessary to avoid voltage lowering in the transfer gate transistor.
When the thickness of the gate oxide film is made thin for the entire chip having the aforementioned elements mounted together, in order to suppress degradation of high speed operation of the peripheral circuits mentioned above, it becomes difficult to ensure reliability of the gate oxide film in the circuits using boosted level Vpp.
Further, a process flow in which thickness of the gate oxide film is changed circuit by circuit makes the process too complicated, hindering reproductivity and reliability.